Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur télécharger pdf (Page 28)

28 UG029, September 6, 2013

Reset Considerations

MAC Soft Reset

When the MAC control register (COMMAND_CONFIG) reset bit is written, the following

functions are executed:

 Ongoing receive is terminated when next possible (graceful stop). A currently

received frame may be written truncated to the FIFO.

 Transmit is disabled when next possible (graceful stop). This may lead to outgoing

frame corruption (frame not terminated but transmit switches to idle

immediately).

 Transmit and Receive are disabled (COMMAND_CONFIG bits 0,1 reset to 0)

 Pause timers are all reset and pause conditions are cleared

 Receive Credit value is cleared (set 0)

 RX and TX FIFOs are reset

 Reset bit clears itself

FIFO / Credit Counter Reset

The receive FIFO credit counter can be initialized by writing the credit value to the MAC

the MAC to begin writing received frame data into the FIFO. As long as the

CREDIT_TRIGGER has not been written, all incoming frames will be discarded.

The credit counter can be re-initialized any time during operation. This will abort any

ongoing receive activity and flush the receive FIFO (discarding frame data if any). Once the

FIFO has been flushed normal receive resumes. An ongoing transaction on the application

interface will be terminated cleanly by producing a final word with EOP and error being

asserted to the application.

PCS Reset

When the PCS control register (CONTROL1) reset bit is written, the following functions are

executed:

 Alignment is lost (for 40G and 100G PCS layers) which eventually leads to local

fault indication to the MAC on XL/CGMII

 Alignment FIFOs are flushed (for 40G and 100G PCS layers)

 All error counters are reset to 0

 Reset bit clears itself

When the reset is issued in 40G mode, the reset causes the 4 lanes of the segment to be reset.

When the reset is issued in 100G mode, the reset causes the 10 lanes used to be reset.

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Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur Page 28