Achronix Speedster22i DDR Manuel d'utilisateur

Speedster22i DDR3 Controller User Guide UG031 – Nov 18, 2014 UG031, Nov 18, 2014 1

enabled, the SIZE parameters and consequently the bus width, are doubled. ddr_int_rd_request 1 Input Read request. ddr_int_rddata [SIZE*4-1:0] Output

External (off-chip) Interface The External DDR interface signals (off-chip) from the DDR PHY to the external memory devices are shown in Table 2 belo

bank DELAY_READ_TO_PRECHARGE 3'h4 4-6 clock cycles Minimum Read to precharge (DDR3 only) DELAY_WRITE_TO_PRECHARGE 4'h8 5-12 clock cycles

is enabled when set to 1 ODT_WRITE_CS0 8'h01 Each bank contains 8 bits, one per DQ. ODT is enabled when set to 1 On die termination selection

Address Mapping The Speedster22i DDR controller contains a specific address bus mapping which is broken down as follows: • Column [colbits-1:0] • B

Write Interface Details The Speedster22i DDR controller contains a simple write interface to the DDR Driver logic.. This uses a 2X clock mode - the

The following timing diagram illustrates a single write command of burst length 4. The signals shown in the following diagrams are ports at the (‘dd

ddr_int_wrdata_req_early_alignClk_div2ddr_int_wr_ requesta0ddr_int_addr[33:0]ddr_int_busy_alignddr_int_wrdata_reqddr_int_ wrdata[287:0]Valid Write com

Figure 7: Write Protocol Timing Diagram (SDRAM Interface) To request a write data transaction, the DDR driver logic (user RTL) must assert ‘ddr_int_

Back-to-Back Write Protocol 2X Clock Mode The following timing diagram (Figure 8) illustrates the same three cascaded, back-to-back write commands. E

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...Timing relationship between ddr_int_wr_request assertion and ddr_int_wrdata_req_early assertion based on AL/CL configuration settings, refresh s

column address provided by the user for the given write request. For DDR3, since ‘ddr_int_burst_size’ is set as a multiple of 4, the user should alwa

DDR Interface Logic(User RTL)Speedster22i DDRControllerddr_int_wr_requestddr_int_addr[33:0]ddr_int_burst_size[7:0]ddr_int_busy_alignddr_int_wrdata_req

As shown above, the wrdata_req signal needs to be asserted for one clock cycle, and in the subsequent clock cycle the write data [575:0] is provided.

Figure 12: Read Interface 2X Clock Mode The following timing diagram illustrates a single read command of burst length 4. The signals shown in the

The Corresponding external (off-chip) interface timing signals are shown in the Figure 14 below. Figure 14: External Interface Read Protocol Timing D

a0a1a2 Valid Write commands after 5 cyclesclockddr_int_rd_requestddr_int_addr[33:0]ddr_int_busyddr_int_rddata_validddr_int_burst_size [7:0]...

trip delay of accessing as well as actually reading from the memory address. The read data is accompanied by a valid signal, denoted ‘ddr_int_rddata_

The read requests are subject to the controller being busy (‘ddr_int_busy_align’). The DDR controller supports burst length option BL8. Each burst wi

To request a read data transaction, the DDR driver (user) logic must assert ‘ddr_int_rd_request’ along with a corresponding address (‘ddr_int_addr [3

Table of Contents Table of Figures ... 4 Features ...

Memory Interface Latency Depending on the data rate and the mode (width) used, the write and read latency for the DDR3 controller will vary. Table 4

Customization using ACE Figure 19 below shows the ACE interface which allows customization of the DDR macro. Users can configure the parameter setting

Revision History The following table shows the revision history for this document. Date Version Revisions 3/29/2013 1.0 Initial Draft Document 4/1

Table of Figures Figure 1: Location of Speedster22i DDR Controllers and PHYs ... 5 Figure

Overview Achronix’s Speedster22i FPGAs contain up to six embedded DDR controllers which can be used to interface with and control off-chip DDR2 or DDR

Features The features supported by the embedded DDR controllers are highlighted below: • 1866 Mbps data rate • The controller and PHY can run at 106

Introduction Speedster22i devices contain up to six embedded (Hardened) DDR Controllers. The instantiatable macros for these are called ‘ddr3_xSIZE1_

The embedded DDR controller macro function performs: • All required initialization sequences such as the programming of AL and CL values based on us

Interfaces Internal (core) Interface The internal interface to the PHY/DDR controller, which is implemented in the core fabric, contains the following