Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur Page 68
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68 UG029, September 6, 2013
7
PAUSE_FWD
Terminate / Forward Pause Frames. If set to '1', pause
frames are forwarded to the user application. If set to '0'
(Reset value), pause frames are terminated and
discarded within the MAC.
8
PAUSE_IGNORE
Ignore Pause Frame Quanta. If set to '1', received pause
frames are ignored by the MAC. If set to '0' (Reset
value), the transmit process is stopped for the amount of
time specified in the pause quanta received within a
pause frame.
This bit is relevant only when PFC_MODE=0.
9
TX_ADDR_INS
Set Source MAC Address on Transmit. If set to '1', the
MAC overwrites the source MAC address received from
the client interface with the MAC address programmed in
registers MAC_ADDR_0 and MAC_ADDR_1 . If set to '0'
(Reset value), the source MAC address from the client
interface is transmitted unmodified to the line.
10
LOOPBACK_EN
Enable PHY Interface Loopback. If set to '1', the signal
loop_ena<n> is set to '1'. If set to '0' (Reset value), the
signal loop_ena<n> is set to '0'.
11
TX_PAD_EN
Enable Transmit Padding. If set to '1' (Reset value), the
MAC transmit logic inserts padding bytes to always
generate frames with a minimum length of 64 bytes with
CRC or 60 bytes without CRC. If set to '0', the MAC
transmit logic can send unpadded frames.
Note: If TX_PAD_EN=0 in 40G and 100G mode of
operation, the MAC does not insert padding bytes for
frames equal or larger than 32 bytes, frames smaller
than 32 bytes are always padded. If TX_PAD_EN=0 in
10G mode of operation, the MAC can send short
unpadded frames of any size.
12
SW_RESET
Self-Clearing Software Reset. When written with '1', all
Statistics Counters are reset to 0.
13
CMD_FRAME_ENA
Enable Reception of all Command Frames. If set to '1',
all command frames are accepted. If set to '0' (Reset
Value), only Pause frames are accepted and all other
command frames are rejected.
A command or control frame is defined as having a MAC
address of 01-80-c2-00-00-01 and type of 0x8808 and
an opcode field that does not match the pause opcode.
14
RX_ERR_DISC
Enable Receive Errored Frame Discard. If set to ‘1’, any
frame received with an error is discarded in the Core and
not forwarded to the client interface. If set to ‘0’ (Reset
value), errored frames are forwarded to the client
interface with ff_rx_err asserted.
Note: Not available in this implementation.
15
PHY_TXENA
Enable PHY Transmit. If set to '1', the signal
phy_txena<n> is set to '1'. If set to '0' (Reset value),
the signal phy_txena<n> is set to '0'.
16
SEND_IDLE
Force Idle Generation. If set to '1', the MAC permanently
sends XL/CGMII Idle sequences even when faults are
received.
- Speedster22i 10/40/100 1
- Gigabit Ethernet User Guide 1
- Copyright Info 2
- Table of Contents 3
- Table of Figures 7
- Overview 8
- Functional Description 10
- Interface Signal List 12
- Global Signals 13
- Receive FIFO Interface 13
- Transmit FIFO Interface 15
- PMA TX/RX Interface 16
- Signal Name 17
- Serial Bus Interface 18
- SerDes (off-chip) Interface 19
- Transmitted Frame Status 19
- Timestamp Timer 19
- MAC/PCS Status Indications 20
- Implementation with ACE 21
- Simulation 24
- .vp or .ve file extenstion 25
- .vma file extenstion 25
- Clock Distribution 26
- Reset Considerations 28
- Fabric FIFO Interface 29
- Credit Handling 32
- Data Structure 33
- Valid Bytes 34
- Byte Number 36
- Frame Status 42
- FIFO Thresholds 43
- FIFO nearly full 44
- FIFO has at least 44
- FIFO is full 44
- Flow Control Interface 45
- Transmit Pause/PFC Operation 47
- Receive Pause/PFC Operation 47
- Write Operation 50
- PMA Management Interface 51
- Power State Sequencing 53
- Auto-Negotiation 54
- Function 55
- Related 55
- Registers 55
- IEEE 1588 Timestamping 58
- Channelized MAC Registers 61
- Transmitted 64
- Bit Name 70
- 1000Base-X / SGMII PCS 71
- Global Registers 77
- Channelized PCS Registers 79
- Auto-Negotiation Registers 87
- PMA Registers 93
- 1A[7:4] 95
- 1B[3:0] 95
- 1B[6:4] 95
- 1C[7:3] 95
- +1 is 4’h9 96
- 51[3:2] 97
- 53[2:2] 97
- 53[3:3] 97
- 8[6:6] 99
- 21[5:1] 99
- 23[5:1] 99
- 25[2:0] 99
- UG029, September 6, 2013 101
- Statistics Data Registers 102
- Receive Statistics Vector 103
- Description 104
- Transmit Statistics Vector 105
- References 107
- Revision History 108
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