Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur Page 15
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UG029, September 6, 2013
15
SFD of the frame.
Valid with ff_rx_sop. The receive timestamp
ff_rx_ts[31:0] can be mapped to any segment of FIFO
group 0 (10G: SEG0-3, 40G: SEG0, 100G: SEG0).
ff_rx_preamble_val
Out
Receive Frame Preamble Valid Indication. Asserted (set to
1) to indicate that a valid preamble is available on pin
ff_rx_preamble[55:0].
Note: Since the signal ff_rx_preamble_val is not a
pulse, the application should sample
ff_rx_preamble[55:0] when ff_rx_sop is set to 1.
ff_rx_preamble[55:0]
Out
Receive Frame Preamble. 56-Bit preamble of the current
frame, valid when ff_rx_preamble_val is set to 1. The
receive frame preamble ff_rx_preamble[55:0] can be
mapped to any segment of FIFO group 0 (10G: SEG0-3,
40G: SEG0, 100G: SEG0).
Transmit FIFO Interface
Table 3 – Transmit FIFO Interface (all synchronous to ff_tx_clk[2:0])
Signal Name
Mode
Description
ff_tx_data
[767:0]
In
Transmit Data. Refer to the ‘Fabic FIFO Interface’ for the
details of how to map this 768-bit bus to the individual
10/40/100G channels.
ff_tx_wren[11:0]
In
Transmit Data Write Enable per segment. Asserted by the
Transmit application to write data into the MAC Core FIFO.
ff_tx_sop[11:0]
In
Transmit Start of Frame per segment. Set to 1 when the
first data word of a frame is driven on ff_tx_data.
ff_tx_eop[11:0]
In
Transmit End of Frame per segment. Set to 1 when the
final data word of a frame is driven on ff_tx_data.
ff_tx_mod
[(12*6)-1:0]
In
Transmit Word Modulo per segment. Indicates which
portion of the final frame word is valid:
Bit 543210
000000 : ff_tx_data[63:0]/[255:0]/[511:0] is
valid (for 10/40/100G)
000001 : ff_tx_data[7:0] is valid
000010 : ff_tx_data[15:0] is valid
000011 : ff_tx_data[23:0] is valid
000100 : ff_tx_data[31:0] is valid
000101 : ff_tx_data[39:0] is valid
000110 : ff_tx_data[47:0] is valid
000111 : ff_tx_data[55:0] is valid
001000 : ff_tx_data[63:0] is valid (40/100G only)
001001: ff_tx_data[71:0] is valid (40/100G only)
.....
.....
011110: ff_tx_data[239:0] is valid (40/100G only)
011111: ff_tx_data[247:0] is valid (40/100G only)
100000: ff_tx_data[255:0] is valid (100G only)
100001: ff_tx_data[263:0] is valid (100G only)
.....
.....
111110: ff_tx_data[495:0] is valid (100G only)
- Speedster22i 10/40/100 1
- Gigabit Ethernet User Guide 1
- Copyright Info 2
- Table of Contents 3
- Table of Figures 7
- Overview 8
- Functional Description 10
- Interface Signal List 12
- Global Signals 13
- Receive FIFO Interface 13
- Transmit FIFO Interface 15
- PMA TX/RX Interface 16
- Signal Name 17
- Serial Bus Interface 18
- SerDes (off-chip) Interface 19
- Transmitted Frame Status 19
- Timestamp Timer 19
- MAC/PCS Status Indications 20
- Implementation with ACE 21
- Simulation 24
- .vp or .ve file extenstion 25
- .vma file extenstion 25
- Clock Distribution 26
- Reset Considerations 28
- Fabric FIFO Interface 29
- Credit Handling 32
- Data Structure 33
- Valid Bytes 34
- Byte Number 36
- Frame Status 42
- FIFO Thresholds 43
- FIFO nearly full 44
- FIFO has at least 44
- FIFO is full 44
- Flow Control Interface 45
- Transmit Pause/PFC Operation 47
- Receive Pause/PFC Operation 47
- Write Operation 50
- PMA Management Interface 51
- Power State Sequencing 53
- Auto-Negotiation 54
- Function 55
- Related 55
- Registers 55
- IEEE 1588 Timestamping 58
- Channelized MAC Registers 61
- Transmitted 64
- Bit Name 70
- 1000Base-X / SGMII PCS 71
- Global Registers 77
- Channelized PCS Registers 79
- Auto-Negotiation Registers 87
- PMA Registers 93
- 1A[7:4] 95
- 1B[3:0] 95
- 1B[6:4] 95
- 1C[7:3] 95
- +1 is 4’h9 96
- 51[3:2] 97
- 53[2:2] 97
- 53[3:3] 97
- 8[6:6] 99
- 21[5:1] 99
- 23[5:1] 99
- 25[2:0] 99
- UG029, September 6, 2013 101
- Statistics Data Registers 102
- Receive Statistics Vector 103
- Description 104
- Transmit Statistics Vector 105
- References 107
- Revision History 108
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