Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur télécharger pdf (Page 25)

UG029, September 6, 2013

Figure 5: Simulation Flow

Software simulation can be done pre-tool chain at the functional RTL level, post-synthesis at

the gate level, and post-route at the Achronix technology specific level.

Throughout the flow, various checkpoints can be done to insure that the design functionality

is kept intact. Figure 5 shows what files are generated at each step and how they are used in

the simulation framework.

At the RTL Design Description level, the FPGA designer’s behavioral RTL description is

compiled by the simulator.

At the Mapped Netlist level, the output of the synthesis tools (Synplify Pro

TM)

) is used. This

is the synchronous gate-level constructs that Achronix Speedster22i understands. It is a

Verilog netlist file that has have a *.vma extension.

At the Post P&R Netlist level, the output of the Achronix CAD Environment (ACE) will

generate a *_routed.vp or *_routed.ve netlist for simulation. This will exist in the project and

active implementation directory under “output”. This file is encrypted using the IEEE STD

1364-2005 Verilog encryption standard, but this file can be decrypted correctly by supported

simulators.

.vp or .ve file extenstion

.vma file extenstion

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Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur Page 25