Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur télécharger pdf (Page 77)

UG029, September 6, 2013

Global Registers

Core Configuration Registers

The Core Configuration Registers are located on register page 12 (0x3000). The register map

of the core configuration registers is shown below.

Table 43 – Core Configuration Register Map

Reg

Addr

(hex)

Type

Description

ACT_CTL_SEG

11:0: Active segment control (1 bit per segment).

0: segment is inactive (Reset value)

1: segment is active

Bits 31:12 are unused and always set to ‘0’.

MODE_CTL_SE

23:0: Segment mode control (2 bits per segment;

(1:0)=SEG0, (3:2)=SEG1, …, (23:22)=SEG11).

00: segment is in 10G mode (Reset value)

01: segment is in 40G mode

10: segment is in 100G mode

11: reserved

Only segments 0, 4 or 8 can be set in 40G mode.

Only segment 0 can be set in 100G mode.

Bits 31:24 are unused and always set to ‘0’.

TXCLK_CTL_SE

23:0: PMA Transmit Clock Selection control (2 bits per

segment; (1:0)=SEG0, (3:2)=SEG1, …,

(23:22)=SEG11). This register reflects the setting of

the output pins sd_tx_clk_ctrl(23:0).

00: 525.625 MHz (Auto-negotiation)

01: 125 MHz (1G mode of operation)

10: 515.625 MHz (10/40/100G mode of operation)

11: reserved

Bits 31:24 are unused and always return ‘0’ on read.

reserved

unused

TX_PRMBL_CTL

_SEG

23:0: User defined Tx preamble control (2 bits per

segment; (1:0)=SEG0, (3:2)=SEG1, …,

(23:22)=SEG11).

00: use default preamble (Reset value)

01: use TX_PREAMBLE_{1,0} register value

10: use ff_tx_preamble input signals

11: reserved

Only segments 0, 1, 2 or 3 can be set to “10” to use

the ff_tx_preamble input signals. It is up to the user

application to ensure that “10” is not set for more than

1 segment.

Bits 31:24 are unused and always set to ‘0’.

RX_PRMBL_CTL

_SEG

3:0: User defined Rx preamble control (1 bit per

segment).

0: do not extract Rx preamble into ff_rx_preamble

1: extract Rx preamble into ff_rx_preamble

Only segments 0, 1, 2 or 3 can be set to “1” to use the

ff_rx_preamble output signals. It is up to the user

application to ensure that “1” is not set for more than 1

segment.

Bits 31:4 are unused and always set to ‘0’.

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 107 108

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Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur Page 77

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