Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur Page 3
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
UG029, September 6, 2013
3
Table of Contents
Copyright Info .................................................................................................... 2
Overview ............................................................................................................ 8
Functional Description .................................................................................... 10
Interface Signal List ........................................................................................ 12
Interface Signal Descriptions ......................................................................... 13
Global Signals .............................................................................................................................. 13
Receive FIFO Interface ................................................................................................................ 13
Transmit FIFO Interface ............................................................................................................... 15
PMA TX/RX Interface ................................................................................................................... 16
Priority Flow Control Interface ...................................................................................................... 17
Auto-Negotiation Control and Status ............................................................................................ 18
Serial Bus Interface ...................................................................................................................... 18
SerDes (off-chip) Interface ........................................................................................................... 19
Transmitted Frame Status ............................................................................................................ 19
Timestamp Timer ......................................................................................................................... 19
MAC/PCS Status Indications ........................................................................................................ 20
Implementation with ACE ............................................................................... 21
Software/Hardware Requirements ....................................................................................... 21
Creating an Ethernet Instance ............................................................................................. 21
Configuring the 10/40/100G Ethernet Core .................................................................................. 21
FPGA Fabric Interface ................................................................................................................. 24
PHY Interface ............................................................................................................................... 24
Interface the Ethernet Core to the FPGA Fabric .................................................................. 24
Data ............................................................................................................................................. 24
Serial Bus Interface ...................................................................................................................... 24
Simulation ............................................................................................................................ 24
Clock Distribution ........................................................................................... 26
Reset Considerations ...................................................................................... 28
MAC Soft Reset ................................................................................................................... 28
FIFO / Credit Counter Reset ................................................................................................ 28
PCS Reset ........................................................................................................................... 28
- Speedster22i 10/40/100 1
- Gigabit Ethernet User Guide 1
- Copyright Info 2
- Table of Contents 3
- Table of Figures 7
- Overview 8
- Functional Description 10
- Interface Signal List 12
- Global Signals 13
- Receive FIFO Interface 13
- Transmit FIFO Interface 15
- PMA TX/RX Interface 16
- Signal Name 17
- Serial Bus Interface 18
- SerDes (off-chip) Interface 19
- Transmitted Frame Status 19
- Timestamp Timer 19
- MAC/PCS Status Indications 20
- Implementation with ACE 21
- Simulation 24
- .vp or .ve file extenstion 25
- .vma file extenstion 25
- Clock Distribution 26
- Reset Considerations 28
- Fabric FIFO Interface 29
- Credit Handling 32
- Data Structure 33
- Valid Bytes 34
- Byte Number 36
- Frame Status 42
- FIFO Thresholds 43
- FIFO nearly full 44
- FIFO has at least 44
- FIFO is full 44
- Flow Control Interface 45
- Transmit Pause/PFC Operation 47
- Receive Pause/PFC Operation 47
- Write Operation 50
- PMA Management Interface 51
- Power State Sequencing 53
- Auto-Negotiation 54
- Function 55
- Related 55
- Registers 55
- IEEE 1588 Timestamping 58
- Channelized MAC Registers 61
- Transmitted 64
- Bit Name 70
- 1000Base-X / SGMII PCS 71
- Global Registers 77
- Channelized PCS Registers 79
- Auto-Negotiation Registers 87
- PMA Registers 93
- 1A[7:4] 95
- 1B[3:0] 95
- 1B[6:4] 95
- 1C[7:3] 95
- +1 is 4’h9 96
- 51[3:2] 97
- 53[2:2] 97
- 53[3:3] 97
- 8[6:6] 99
- 21[5:1] 99
- 23[5:1] 99
- 25[2:0] 99
- UG029, September 6, 2013 101
- Statistics Data Registers 102
- Receive Statistics Vector 103
- Description 104
- Transmit Statistics Vector 105
- References 107
- Revision History 108
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