Achronix Speedster22i 10G/40G/100G Ethernet Manuel d'utilisateur télécharger pdf (Page 10)

10 UG029, September 6, 2013

Functional Description

Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram

On the FPGA Fabric interface side, the 10/40/100 Gigabit Ethernet MAC and PCS Core

implements a flexible FIFO interface that can be connected to a custom user application.

On the Ethernet line side, the Core implements a 12 x 20-Bit line interface to the Physical

Media Attachment (PMA) module which consists of 12 x 10G SerDes lanes directly connected

to the FPGA I/O pins. The 12 SerDes lanes in the PMA module can be utilized independently

of the 10/40/100G Ethernet MAC. The physical interface for this module in configured via the

10/40/100G Ethernet MAC IP configuration wizard. Details of the Achronix SerDes I/O are

beyond the scope of the user guide. A separate user guide is available for the SerDes I/O

functionality.

X/XL/CGMII Loopbacks

Each PCS Layer implements a X/XL/CGMII side loopback to the MAC, which returns all data

from the MAC transmit back to the MAC receive side without passing through any of the

PCS blocks.

When the loopback is enabled the transmitted data is treated depending on the mode of

operation as follows:

 10G Base-R: The PCS transmits the constant pattern of 0x00ff (8x'1' bits alternating

with 8x'0' bits) to the SerDes line interface.

 40G/100G Base-R: The PCS transmits the MAC transmit data unchanged to the SerDes

line interface (as defined by IEEE802.3ba).

FPGA Fabric

Interface

10/40/100

Gigabit Ethernet

Hard IP Core

sbus

12 RX

SerDes

Lanes

12 TX

SerDes

Lanes

Media

Access

Controller

(MAC)

Physical

Coding

Sublayer

(PCS)

RX FIFO

TX FIFO

Configuration / Control / Statistics

Physical

Media

Attachment

(PMA)

JTAG

Physical

Interface

(PHY)

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 107 108

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