
Registers DFFES
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 60
DFFES
Positive Clock Edge D-Type Register with Clock Enable and
Asynchronous/Synchronous Set
Figure 2-6: Logic Symbol
DFFESisasi
ngleD‐typeregisterwithdatainput(d),clockenable(ce),clock(ck),andactive‐
low set (sn) inputs and data (q) output. The active‐low set input overrides all other inputs
whenitisassertedlowandsetsthedataoutputhigh. Theresonseoftheqoutputinresponse
totheas
sertedsetdependsonthevalueofthesr_assertionparameterandisdetailedinTable
2‐19: DFFES Function Ta
ble when sr_assertion = “unclocked” and Table 2‐20: DFFES
FunctionTablewh
ensr_assertion=“clocked”.Ifthesetinputisnotasserted,thedataoutput
issettotheva
lueonthedatainputupon thenextrising edgeof theclockifthe active‐high
clockenableinputisasserted.
Pins
Table 2-17: Pin Descriptions
Name Type Description
d Data input.
sn
Active-low asynchronous/
synchronous set input. A low on sn sets the q
output high independent of the other inputs if the sr_assertion parameter
is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a low
on rn sets the q output high at the next rising edge of the clock.
ce Active-high clock enable input.
ck Positive-edge clock input.
q
Data output. The value pr
esent on the data input is transferred to the q
output upon the rising edge of the clock if the clock enable input is high
and the reset input is high.
Parameters
Table 2-18: Parameters
Parameter Defined Values Default Value
init 1’b1
sr_assertion “unclocked”
init
The init parameter defines the initial value of the output of the DFFES register.This is the
valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue
oftheinitparameteris1’b1.
input
input
input
input
output
1’b0, 1’b1
“unclocked”, “clocked”
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