Achronix Speedster22i User Macro Guide Manuel d'utilisateur Page 115
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Memories BRAM80K
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 98
Table 6-12: Mapping of Word Sizes to the Native 2048x40 Memory Locations
Port
Width
Extended
Parity Bits
Parity
Bits
Data Bits
40 0 0 0
36 n/a 0 0
32 n/a 0
20 1 0 1 0 1 0
18 n/a 1 0 1 0
16 n/a 1 0
10 3 2 1 0 3 2 1 0 3 2 1 0
9 n/a 3 2 1 0 3 2 1 0
8 n/a 3 2 1 0
5 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
4 n/a 7 6 5 4 3 2 1 0
2 n/a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 n/a 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8 7 6 5 4 3 2 1 0
Read and Write Operations
TheBRAM80Khasfourbasicmodesofreadandwriteoperations:
•Write‐Fi
rst,LatchedMode
•Write‐Fi
rst,RegisteredMode
•No‐Change,LatchedMode
•No‐Change,Register
edMode
One of the
se four modes is selected for Port A(Port B) via the
porta_write_mode(portb_write_mode)andporta_en_out_reg(portb_en_out_reg)parameters.
Read Operation
There are two modes of operation supported for reading data from the BRAM80K: latched
modeandregistermode.Inlatchedmode,thereadaddressisregisteredandthestoreddatais
latched into the output latches. In the registered mode, the read op eration results in one
additionalcycleoflatency.
Write Operation
The write operation is a single clock edge operation. The addra(addrb) write address is
registeredandthedina(dinb)datainputisstoredintheBRA M80Katthenextactiveedgeof
thewriteclock.Theporta_write_mode(portb_write_mode)parametercontrolswhatisoutput
on the douta(doutb) output during a write operation. If the
porta_
write_mode(portb_write_mode)parameterissetto“no_change”,thedouta(doutb)will
remain unchanged during a write operation on port A(B). If the
porta_write_mode(portb_write_mode) parameter is set to “write_first”, the value of
douta(doutb)output willbeupdatedwiththedina(dinb)dataiftheappropriatebyteenable
inputisenabled.
- Speedster22i 1
- Macro Cell Library 1
- Copyright Info 2
- Table of Contents 3
- Introduction 15
- Cell Naming Conventions 16
- Item Format Examples 17
- Chapter 1 – I/O Cells 18
- Bidirectional I/O Pad 19
- Set/Reset 21
- I/O Cells IOPAD_D 23
- IOPAD_D2 26
- Non-Registered Input Pad 30
- I/O Cells IPAD_D2 36
- IPAD_DIFF 37
- IPAD_DIFFD 39
- IPAD_DIFFD2 41
- I/O Cells IPAD_DIFFD2 43
- Non-Registered Output Pad 44
- I/O Cells OPAD_D 47
- I/O Cells OPAD_D2 50
- OPAD_DIFF 52
- OPAD_DIFFD 54
- I/O Cells OPAD_DIFFD 55
- OPAD_DIFFD2 57
- I/O Cells OPAD_DIFFD2 58
- I/O Cells TPAD_D 63
- Chapter 2 – Registers 65
- Synchronous Clear 69
- Synchronous Preset 71
- Inputs Output 74
- Asynchronous/Synchronous Set 76
- Chapter 3 – Logic Functions 99
- VHDL Instantiation Template 100
- Four Input Lookup Table 101
- Parameters 101
- Name Type Description 103
- Chapter 6 – Memories 106
- BRAM80K Pins 107
- Memories BRAM80K 109
- Read and Write Operations 115
- Timing Diagrams 117
- Memory Initialization 118
- PAGE 102 119
- PAGE 103 120
- PAGE 104 121
- PAGE 105 122
- PAGE 106 123
- PAGE 107 124
- PAGE 108 125
- PAGE 109 126
- PAGE 110 127
- PAGE 118 135
- BRAM80KFIFO 136
- Name Type 137
- Description 137
- Memories BRAM80KFIFO 139
- PAGE 122 139
- PAGE 123 140
- PAGE 124 141
- PAGE 125 142
- PAGE 126 143
- Selected Input for Write 144
- Write Pointer Reset Use Model 144
- PAGE 128 145
- PAGE 129 146
- PAGE 130 147
- PAGE 131 148
- PAGE 132 149
- Read and Write Count Outputs 150
- Status Flags 151
- Flag Latency 152
- Optional Output Register 153
- FIFO Operational Modes 154
- FIFO Operations 155
- PAGE 140 157
- BRAM80KECC 164
- BRAM80KECC Pins 165
- Memories BRAM80KECC 166
- PAGE 149 166
- PAGE 150 167
- BRAM80KECC Modes of Operation 168
- BRAM80KECCFIFO 170
- LRAM640 Pins 174
- Memories LRAM640 175
- PAGE 158 175
- LRAM640 Memory Initialization 176
- LRAMFIFO 177
- parameteris7’h04, 181
- Write Error Flag 183
- Read Error Flag 183
- Chapter 7 – Multipliers 188
- Inputs Outputs 189
- BMACC56 Pins 190
- Multipliers BMACC56 193
- PAGE 176 193
- PAGE 177 194
- PAGE 178 195
- PAGE 179 196
- PAGE 180 197
- PAGE 181 198
- PAGE 182 199
- BMULT28X28 200
- Chapter 8 – Special Functions 201
- ACX_DESERIALIZE 203
- Speedster Macro Cell Library 204
- PAGE 187 204
- ACX_CLKGEN 205
- ACX_CLKGEN Pins 206
- Default 208
- ACX_CLKGEN Components 211
- Feedback Divider 212
- Clock Feedback Selection 212
- PLL Control 213
- Serial Control Bus (SCB) 213
- PAGE 197 214
- PAGE 198 215
- PAGE 199 216
- PAGE 200 217
- PAGE 201 218
- PAGE 202 219
- PAGE 203 220
- PAGE 204 221
- PAGE 206 223
- Revision History 224
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