Achronix Speedster22i User Macro Guide Manuel d'utilisateur Page 109
- Page / 224
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Memories BRAM80K
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 92
porta_read_width(portb_read_width)
The porta_read_width(portb_read_width) parameter sets the read width for Port A(B). The
read width may vary from the write port width, but it must be within the allowable
combinations defined in the
Memory Organization and Data Input / Output Pin
Assignmentssection.
porta_write_width(portb_write_width)
Theporta_write_width(porta_write_width)parametersetsthewritewidthforPortA(B).The
read width may vary from the write port width, but it must be within the allowable
combinations defined in the
Memory Organization and Data Input / Output Pin
Assignmentssection.
porta_write_mode(portb_write_mode)
The porta_write_mode(portb_write_mode) parameter is used to define the response of the
Port A(B) output to write operations. If porta_write_mode(portb_write_mode) is set to
“no_change”, douta(doutb) will remain unchanged during write operations. If
porta_write_mode(portb_write_mode) is set to “write_first”, the data present on the
dina(dinb) input during the write operation will appear on the
output of Port A(B) if the
appropriatewriteenablebit, wea(web),ishigh.NotethattheBRAM80Kdoesnot supporta
‘read‐first’ or ‘read‐before‐write’ mode. If this behavior is detected by synthesis, a warning
willbeissuedinthesynthesislogfileandaregisterfilewill
besynthesized.Toimplementa
more efficient mapping of a ‘read‐first’ memory, the user should updat e his code to use an
AchronixBRAM 80K_READ_FIRSTsoftmacro.Pleasereferto
SupportforRead‐First(Read‐
Before‐Write)MemoryOperationsforafurtherexplanationofread‐firstmemorysupport.
porta_clock_polarity(portb_clock_polarity)
Theporta_clock_polarity(portb_clock_polarity)parameterisusedtosettheactiveedgeofthe
PortA(B)clock.Avalueof“rise”correspondstoanactiverisingedgeassignmentwhile“fall”
corresponds to an act ive falling edge assignment. The default value of the
porta_clock_polarity(portb_clock_polarity)is“rise”.
porta_peval(portb_peval)
Theporta_peval(p ortb_peval)parameterdefinestheactivelevelofthePortA(B)pea(peb)port
enableinput.Assigningavalueof1’b0toporta_peval(portb_peval)configuresthePortA(B)
pea(peb) port enable input to be active low, while an assignmentto1’b1setsan active‐high
level.Thedefaultvalueoftheporta_peval(portb_peval)parameter
is1’b1.
porta_latch_rstval(portb_latch_rstval)
Theporta_latch_rstval(portb_latch_rstval)parameterdefinestheactivelevelofthe PortA(B)
output latch reset input. Assigning a value of 1’b0 to porta_latch_rstval(portb_latch_rstval)
configuresthePortA(B)outputlatchtohaveanactive‐lowsynchronousreset,whileassigning
avalueof1’b1configuresthePortA(B)outputlatchtohaveanactive
‐highsynchronousreset.
Thedefaultvalueofporta_lat ch_rstval(portb_latch_rstval)is1’b1.
porta_en_out_reg(portb_en_out_reg)
Theporta_en_out_reg(portb_en_out_reg)parameterdetermineswhetherthePortA(B)output
registerisenabled.Avalueof1’b0disablestheoutputregisterandresultsinareadlatencyof
onecycle,whileavalueof1’b1enablestheoutputregisterandresultsinareadlatencyoftwo
cycles.Thedefaultvalueof
theporta_en_out_reg(portb_en_out_reg)parameteris1’b0.
- Speedster22i 1
- Macro Cell Library 1
- Copyright Info 2
- Table of Contents 3
- Introduction 15
- Cell Naming Conventions 16
- Item Format Examples 17
- Chapter 1 – I/O Cells 18
- Bidirectional I/O Pad 19
- Set/Reset 21
- I/O Cells IOPAD_D 23
- IOPAD_D2 26
- Non-Registered Input Pad 30
- I/O Cells IPAD_D2 36
- IPAD_DIFF 37
- IPAD_DIFFD 39
- IPAD_DIFFD2 41
- I/O Cells IPAD_DIFFD2 43
- Non-Registered Output Pad 44
- I/O Cells OPAD_D 47
- I/O Cells OPAD_D2 50
- OPAD_DIFF 52
- OPAD_DIFFD 54
- I/O Cells OPAD_DIFFD 55
- OPAD_DIFFD2 57
- I/O Cells OPAD_DIFFD2 58
- I/O Cells TPAD_D 63
- Chapter 2 – Registers 65
- Synchronous Clear 69
- Synchronous Preset 71
- Inputs Output 74
- Asynchronous/Synchronous Set 76
- Chapter 3 – Logic Functions 99
- VHDL Instantiation Template 100
- Four Input Lookup Table 101
- Parameters 101
- Name Type Description 103
- Chapter 6 – Memories 106
- BRAM80K Pins 107
- Memories BRAM80K 109
- Read and Write Operations 115
- Timing Diagrams 117
- Memory Initialization 118
- PAGE 102 119
- PAGE 103 120
- PAGE 104 121
- PAGE 105 122
- PAGE 106 123
- PAGE 107 124
- PAGE 108 125
- PAGE 109 126
- PAGE 110 127
- PAGE 118 135
- BRAM80KFIFO 136
- Name Type 137
- Description 137
- Memories BRAM80KFIFO 139
- PAGE 122 139
- PAGE 123 140
- PAGE 124 141
- PAGE 125 142
- PAGE 126 143
- Selected Input for Write 144
- Write Pointer Reset Use Model 144
- PAGE 128 145
- PAGE 129 146
- PAGE 130 147
- PAGE 131 148
- PAGE 132 149
- Read and Write Count Outputs 150
- Status Flags 151
- Flag Latency 152
- Optional Output Register 153
- FIFO Operational Modes 154
- FIFO Operations 155
- PAGE 140 157
- BRAM80KECC 164
- BRAM80KECC Pins 165
- Memories BRAM80KECC 166
- PAGE 149 166
- PAGE 150 167
- BRAM80KECC Modes of Operation 168
- BRAM80KECCFIFO 170
- LRAM640 Pins 174
- Memories LRAM640 175
- PAGE 158 175
- LRAM640 Memory Initialization 176
- LRAMFIFO 177
- parameteris7’h04, 181
- Write Error Flag 183
- Read Error Flag 183
- Chapter 7 – Multipliers 188
- Inputs Outputs 189
- BMACC56 Pins 190
- Multipliers BMACC56 193
- PAGE 176 193
- PAGE 177 194
- PAGE 178 195
- PAGE 179 196
- PAGE 180 197
- PAGE 181 198
- PAGE 182 199
- BMULT28X28 200
- Chapter 8 – Special Functions 201
- ACX_DESERIALIZE 203
- Speedster Macro Cell Library 204
- PAGE 187 204
- ACX_CLKGEN 205
- ACX_CLKGEN Pins 206
- Default 208
- ACX_CLKGEN Components 211
- Feedback Divider 212
- Clock Feedback Selection 212
- PLL Control 213
- Serial Control Bus (SCB) 213
- PAGE 197 214
- PAGE 198 215
- PAGE 199 216
- PAGE 200 217
- PAGE 201 218
- PAGE 202 219
- PAGE 203 220
- PAGE 204 221
- PAGE 206 223
- Revision History 224
© 2020, manymanuals.fr. Tous droits réservés | 0.051 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels