Achronix Speedster22i User Macro Guide Manuel d'utilisateur télécharger pdf (Page 119)

Memories BRAM80K

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 102

When the BRAM80K memory is configured with port widths of 9, 18, or 36 bits wide, the

initialmemorycontentsmay  be defined by initializing the 256 256‐bitparameters initd_000

throughinitd_255andthe32256‐bitparametersinitp_00through initp_31.Eachnine‐bit byte

is configured by programming the

 bottom eight bits of the byte to consecutive bytes of the

initd_000throughinitd_255 parametersandprogrammingtheninthbittoconsecutivebitsof

theinitp_00throughinitp_32parameters.Theparitymemoryisalsoorganizedaslittle‐endian

withthefirstparitybitlocationm appedtobit0ofinitp_00

andthelastparitybitmappedto

thebit255ofinitp_31.

When the BRAM80K memory is configured with port widths of 10, 20, or 40 bits wide, the

initialmemorycontentsmay  be defined by initializing the 256 256‐bitparameters initd_000

through initd_255, the 32 256‐bit parameters initp_00  through initp_31, and the 32 256‐bit

parametersinitpx_00throughinitpx_31.Each

ten‐bitbyteisconfiguredbyprogrammingthe

bottom eight bits of the byte to consecutive bytes of the initd_000 through initd_255

parameters,programmingtheninthbittoconsecutivebitsoftheinitp_00throughinitp_31

parameters and programming the tenth bit to consecutive bits of the initpx_00 through

initpx_31parameters.

Theextendedparitymemoryisalsoorganizedaslittle‐endianwiththe

firstparitybit(tenthbit)locationmappedtobit0ofinitpx_00andthelastparitybitmapped

tothebit255ofinitpx_31.

TheBRAM80 K memoryblock mayalternativelybeinitializedwith amemoryfileby setting

the mem_init_file to point to the path of a memory initialization file. The file format in the

lattercaseisdefinedbyhexadecimalentriesseparatedbywhitespace,wherethe whitespace

is de fined by spaces or

 line separation. Each number is hexadecimal of  width equal to the

maximum value amongst the parameters: porta_read_width, porta_write_width,

portb_read_width,portb_write_width.Anumberentrymaycontainunderscore(_)characters

amongstthedigits,forexample,A234_4567_33.Commentingisallowedfollowingadouble‐

slash (//) through to the end of the line. C‐

like commenting is also allowed where the

charactersbetweenthe/*and*/areignored.Thememoryisinitializedstartingwiththefirst

entryofthefileinitializingthememoryarraystartingwithaddresszero,movingupward.

Ifthemem_init_valueisdefined,theBRAM80Kwillbeinitializedwiththevaluesdefinedin

thefilepointedtobythe mem_init_fileparameter accordingtotheformat definedabove.If

themem_init_file isleftatthe defaultvalueof“”, the initial contentswillbedefinedbythe

values of the

 initd_000‐initd_255, initp_00‐ini tp_31, and the initpx_00‐initpx_31

parameters.Ifthememoryinitializationparametersandthemem_init_fileparametersarenot

defined, the contents of the BRA M80K will not be initialized and the contents will be

unknownuntilthememorylocationsarewritten.

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Achronix Speedster22i User Macro Guide Manuel d'utilisateur Page 119

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