Achronix ACE Version 5.0 Manuel d'utilisateur télécharger pdf (Page 82)

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Editors Chapter 3. Concepts

Overview Page

The Overview page contains the top-level, global properties that govern the structure and base

conﬁguration of the LRAM FIFO.

Figure 3.39: LRAM FIFO IP Editor Overview Page

LRAM FIFO Editor Overview Page Options

Option Description

Clock Mode FIFOs can be conﬁgured in Single Clock mode to use a single clock

domain for writes and reads. Single clock mode bypasses the

synchronization circuitry to enable faster updates to status ﬂags.

Dual Clock mode allows two independent clocks to be used for

reads and writes.

Data Width The FIFO read and write port data width.

Address Depth The FIFO address depth is the total number of writable data words

in the FIFO.

Flag Settings

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