Achronix ACE Version 5.0 Manuel d'utilisateur télécharger pdf (Page 26)

Editors Chapter 3. Concepts

Output Divider [0,1,2,3] Pages

The Output Divider pages contain conﬁguration information relating to the output divider (OD) of one of

the PLLs clock output signals. Since there are one-to-four PLL output signals per PLL, there are also up to

four of these pages. Because the PLL and OD logic may be bypassed on a per-output basis (as conﬁgured

on the Clock Output [0,1,2,3] Pages), this page may sometimes be hidden, even if the related clock output is

enabled.

Figure 3.6: IP Advanced PLL Editor Output Divider 0 Page

PLL Editor Output Divider Page Options

Option Editable

Description

OD[0-3] Input

Frequency

The calculated frequency of the input signal as it enters

this OD logic block.

OD[0-3] Divider Y

The factor by which the signal entering the OD should be

divided before it exits the OD. As this increases, the OD

output frequency decreases. (Unless this OD is in the

external feedback path, in which case increasing this

value does not affect the OD output frequency, but

increases the VCO output frequency.)

OD[0-3] Output

Frequency

The calculated frequency of the output signal as it exits

this OD logic block.

Enable OD[0-3] Phase

Adjustment

Enabling this will allow this OD to perform phase

adjustments on the OD output signal. When enabled, this

activates the related OD [0,1,2,3] Phase Adjustment Pages.

When disabled, the phase adjustment conﬁguration

options remain hidden.

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Achronix ACE Version 5.0 Manuel d'utilisateur Page 26