Achronix ACE Version 5.0 Manuel d'utilisateur télécharger pdf (Page 244)

Reports Chapter 3. Concepts

Timing Report

The Timing Report provides details on how well the current design is meeting timing on the selected device.

Timing analysis can be performed at several stages in the ﬂow, each stage generating a different report. If

the design has not yet been routed, placement and/or routing are estimated.

The Timing Reports will, of course, contain different details based upon whether the chosen target device is

synchronous or asynchronous.

Synchronous Fabrics

(Includes the 22iHD device family.)

This report will contain a Summary section and a Details section.

The Summary section will contain three tables. There will be a table for Critical Setup (max) Timing Paths,

one for Critical Hold (min) Timing Paths, and one for the resulting Clock Frequencies. Each summary

section table will contain a single row for each Clock/Group, showing the most critical path for that

Clock/Group.

The Details section will contain a conﬁgurable maximum number of critical setup paths and critical hold

paths for each Clock/Group, and each of those critical paths will include a conﬁgurable maximum number

of worst paths for the critical path’s endpoint.

The number of critical paths and worst paths are Implementation Options conﬁgured in the Options View

under ”Timing Analysis”.

Asynchronous Fabrics

(Includes the 22iHP, RDR, and SPD device families.)

This report contains three sections, which can be individually enabled and conﬁgured in the Options View

under ”Timing Analysis”.

The three parts of the report are:

• Current Results

• Potential Results

• Clock Domain Details

This report is automatically generated by the Flow during any of the Run . . . Timing Analysis ﬂow steps.

To generate this report manually, see the Tcl command run timing analysis. For details on how this

report can be used to improve design performance, see Analyzing Critical Paths.

Part I: Current Results This part of the report contains the results that match the current XP values (the

default is XP=0). If the bitstream were generated with the current settings and downloaded to the device,

these are the results which would be observed on the Achronix device.

Part II: Potential Results This part of the report shows the potential frequency, obtained with the best

possible XP value. To actually get these results, (to make them the current results,) users will have to set

these XP values with the set extra pipeline command in the implementation’s SDC ﬁle, and then re-

run the ﬂow.

In addition, in the Options View users can indicate that a table with different XP values should be generated.

Part III: Clock Domain Details Suppose a design has clocks c1 and c2 which are related so that c2 is

twice as fast as c1. If timing analysis ﬁnds that c1 is limited to 100MHz, then automatically c2 is limited to

200MHz, even if there is no critical path that directly imposes that limit. In parts I and II of the report, the

c1/c2 clock ratio is always enforced, because that is how the circuit behaves. However, in some cases users

may want to know how fast c2 could run ”by itself”. Such an analysis is provided in Part III of the report:

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