Achronix ACE Version 5.0 Manuel d'utilisateur télécharger pdf (Page 61)

Editors Chapter 3. Concepts

Write

Pointer

Reset

Source

The Write Pointer Reset Source selects the reset source for the write

pointer by conﬁguring the wrrst input mode parameter on the FIFO.

The FIFO macro provides the user with several options to reset the

FIFO either sychronously or to synchronize the reset input to the

appropriate clock domain within the FIFO without the need to

implement separate synchronization circuitry in the FPGA fabric.

Read Reset

Sync Stage

Depth

The Read Reset Sync Stage Depth deﬁnes the number of stages of

registers used to synchronize the rdrst input pin to the wrclk clock

domain if the rdrst signal is used by the Write Pointer Reset. The

value of the rdrst sync stages parameter is only used if the

wrrst input mode is set to 2’b10 or 2’b11.

Read

Pointer

Reset

Source

The Read Pointer Reset Source selects the reset source for the read

pointer by conﬁguring the rdrst input mode parameter on the FIFO.

The FIFO macro provides the user with several options to reset the

FIFO either sychronously or to synchronize the reset input to the

appropriate clock domain within the FIFO without the need to

implement separate synchronization circuitry in the FPGA fabric.

Write

Reset Sync

Stage

Depth

The Write Reset Sync Stage Depth deﬁnes the number of stages of

registers used to synchronize the wrrst input pin to the rdclk clock

domain if the wrrst signal is used by the Read Pointer Reset. The

value of the wrrst sync stages parameter is only used if the

rdrst input mode is set to 2’b10 or 2’b11.

Write Port

Reset

Active-

High

When this is enabled, the write port reset (wrrst) input is active-high.

Otherwise, the write port reset will be active-low.

Read Port

Reset

Active-

High

When this is enabled, the read port reset (rdrst) input is active-high.

Otherwise, the read port reset will be active-low.

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Achronix ACE Version 5.0 Manuel d'utilisateur Page 61

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