Achronix ACE Version 5.0 Manuel d'utilisateur télécharger pdf (Page 261)

Running the Flow Chapter 4. Tasks

ﬁnal simulation netlist can be generated without errors. If your design fails ﬁnal DRC checks, you can still

generate a Post-Route timing report for experimental purposes. However, no bitstream may be generated

to run the design on the hardware unless all ﬁnal DRC checks pass.

Run Sign-off Timing Analysis (Optional)

After Run Final DRC Checks has successfully completed on an implementation, the Run Sign-Off Timing

Analysis step can be run. This step generates and writes a ﬁnal sign-off timing report ﬁle for the placed and

routed design, after all ﬁnal DRC checks have passed. The generated report is automatically displayed in

the editor area upon successful completion. This step is run by default when Run Flow is executed.

Generate Final Simulation Netlist (Optional)

After Run Final DRC Checks has successfully completed on an implementation, the Generate Final

Simulation Netlist step can be run. This step generates and writes an encrypted, post-place-and-route

Verilog simulation netlist ﬁle from the ﬁnal DRC-free design. This netlist may be used to simulate the post-

place-and-route design. This step is not run by default when Run Flow is executed.

FPGA Programming Steps

Generate Bit Stream

After a design is placed and routed, a bitstream for the target device can be generated. This step generates

a bitstream (STAPL ﬁle) for the current implementation based on the settings in the Options view (see the

Options settings for Bitstream Generation). This step is run by default when Run Flow is executed.

FPGA Download

After the bitstream is generated, it is ready for downloading to the FPGA via the Bitporter pod speciﬁed

under the Options view settings (see the Options settings for FPGA Download). This step is not run by

default when Run Flow is executed.

A bitstream can also be downloaded to the FPGA via the Download view (see Playing a STAPL File)

For more details, refer to the Bitporter User Guide (UG004).

Running Multiple Flows in Parallel

Normally, ACE only allows a single project’s implementation to be run through the ﬂow at a time.

Using the Multiprocess View, ACE allows users to run multiple implementations within a single project

through the ﬂow in parallel, via a conﬁgurable number of parallel processes. Executing multiple

implementations in this manner allows ACE to provide a Multiprocess Summary Report of the resulting

frequencies

, permitting the user to make QOR performance comparisons between implementations

utilizing different starting clock constraints, placement constraints, and potential optimizations.

Finding the Multiprocess View

To make use of the Multiprocess View, it must ﬁrst be made visible. (It is hidden by default.) To show

the Multiprocess View, ﬁrst select the Projects Perspective ( ). Then, in the Flow View, select the Show

Multiprocess View ( ) button. This will cause the Multiprocess view to be displayed, and will also

hide/minimize the ACE Editor Area (where reports are displayed) to allow sufﬁcient screen area for the

Multiprocess view. (The next time an ACE report is generated/opened, the ACE Editor Area will again

become visible.)

Alternately, the Multiprocess view may be displayed without side-effects from within any perspective by

selecting Window → Show View → Other. . . → Achronix → Multiprocess.

if the optional Post-Route Timing Analysis or Sign-off Timing Analysis ﬂow steps are enabled

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Achronix ACE Version 5.0 Manuel d'utilisateur Page 261

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