Achronix Speedster22i Snapshot Manuel d'utilisateur télécharger pdf (Page 12)

Clock constraints (SDC file):

###### CLOCK CONSTRAINTS INSIDE .SDC FILE #####

create_clock -period 10ns usr_clk

create_clock –period 40ns snapshot_instance.core_y_tck

##### THIS snapshot_instance.core_y_tck IS AN INTERNAL ######

##### TEST CLOCK GENERATED INSIDE THE SNAPSHOT-MACRO ####

##### BLOCK. IT IS MANDATORY FOR THE USER TO #######

##### CONSTRAINT THIS CLOCK PROPERLY; OTHERWISE #######

##### SNAPSHOT-MACRO WILL NOT WORK ON THE BOARD ########

set_false_path –from usr_clk –to snapshot_instance.core_y_tck

set_false_path –from snapshot_instance.core_y_tck –to usr_clk

NOTES:

1. In ACE there is a Tap-Controller (JTAP) macro embedded inside which meets the

IEEE1149.1 JTAG standard. All the JTAG specific signals get automatically assigned

in ACE during back-end procedure. So that user does not need to assign any

constraints for these JTAG signals.

12 UG016, September 22, 2014

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Achronix Speedster22i Snapshot Manuel d'utilisateur Page 12