Achronix Speedster22i Pin Connections and Power Sequencing Manuel d'utilisateur Page 1

UG042, August 19, 2014 1 Speedster22i Pin Connections and Power Supply Sequencing User Guide UG042 – August 19, 2014

10 UG042, August 19, 2014 the FPGA fabric. regulator. This supply can be shared with VCC and VDD_BRAM. VDD_CFGWL CFG Power Power Supply for the w

UG042, August 19, 2014 11 Power Supplies and Sequencing Power Supply Block Diagram 12V DC Board SupplyPre-Switching RegulatorRegulatorRegulatorVDDL1.

12 UG042, August 19, 2014 Power Sequencing Block Diagram Power Up RequirementsVCC, VDD_CFG, VDD_BRAMVDD_CFGWLVDDO_B[xx] (1.2V/1.5V/1.8V)VDDO_JCF

UG042, August 19, 2014 13 Revision History The following table shows the revision history for this document. Date Version Revisions 04/05/2013 1.0 Ini

2 UG042, August 19, 2014 Copyright Info Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trade

UG042, August 19, 2014 3 Pin Connection Guidelines Please see the table below on guidelines for connecting all IOs on the Speedster22i HD FPGAs. For c

4 UG042, August 19, 2014 IEEE1149.1 JTAG Interface Do not leave JTAG I/Os unconnected. The JTAG interface should be brought out to a JTAG head

UG042, August 19, 2014 5 PROGRAM_ENABLE[1:0] CFG Input Pin enabling the programming of the eFuse for the AES encryption keys, which is done in the man

6 UG042, August 19, 2014 command and programming commands are sent via control registers writes done via the IEEE 1149.1 JTAG interface. In the C

UG042, August 19, 2014 7 feature is used. NOT Available for HD1000. other devices, connect directly to observation point for error. CONFIG_SCRUBBING_E

8 UG042, August 19, 2014 Miscellaneous CORE_TESTIN1 DBG Output Debug interface used for testing the fabric Leave unconnected. EDM DBG Output

UG042, August 19, 2014 9 AVDD_PLL_[SE, SW, NE, NW][3:0] PLL Power Analog power supply for the PLLs feeding the FPGA core fabric. Connect all 1.7V AVDD