Achronix Speedster22i Memory PHY Manuel d'utilisateur télécharger pdf (Page 19)

UG043, April 26, 2014

Mux Output Option

Ph0

Ph1

180

202.5

225

247.5

270

292.5

315

337.5

360

In the second stage the phase interpolator mixes the two phases (ph0 and ph1) mentioned

above to meet the required delay/phase difference. For example, to push out the incoming

signal by a 100 degree phase, the first stage selects phase 90 and phase 112.5, and then the

second stage uses this pair and fine tunes it to meet the required 100 degree push out. Figure

12 below provides a block diagram of the SDLL and Phase Interpolator.

Slave DLL

Course selection of clocks

Through Muxs

Fine Selection through

Programmable drive

strength

Phase Interpolator Block per clock

Pbias

Nbias

Bias from MDLL

Decoder

LSB[3:0]MSB[16:0]

Phase

Interpolator

Codes<5:0>

Phase

Interpolator

Clock out

Figure 12: SDLL and Phase Interpolator Block Diagram

1 2 ... 14 15 16 17 18 19 20

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Achronix Speedster22i Memory PHY Manuel d'utilisateur Page 19